1. Technical Field
The present invention relates to a method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same. More particularly, the present invention relates to a method for arranging memories of a low-complexity LDPC decoder and a low-complexity LDPC decoder using the same that feature low power consumption.
2. Description of Related Art
Recently, many encoding methods have been proposed for use in communication and storage systems. Low-density parity-check (LDPC) codes, in particular, have good performance in error detection and correction and can be decoded at very high speed. Quasi-cyclic LDPC codes are now mostly discussed since their parity-check matrices are composed of several regular circulant matrices and are very suitable for hardware implementation. However, in order to obtain better decoding performance, the size of the parity-check matrices is usually large and thus they must be used in conjunction with decoders having large-capacity memories.
In a conventional quasi-cyclic LDPC decoder that has a partially parallel architecture, the memory is typically divided into several memory blocks based on circulant matrices so that the operation processing units (including check node units and variable node units) can read or write data from or to the memory blocks simultaneously. Thus, not only is parallelism of operations of the LDPC decoder enhanced, but also the memory access problems associated with block rows and block columns are prevented.
Nevertheless, as the number of circulant matrices that form an LDPC matrix increases, the number of memory blocks required also increases. According to the principle of memory design, given the same total memory capacity, the memory area composed of small-capacity memory blocks is larger than that composed of large-capacity memory blocks. This explains why an LDPC decoder having a large number of small-capacity memory blocks cannot be effectively downsized. Moreover, from the perspective of hardware design, a large number of small-capacity memory blocks lead to high hardware costs and high power consumption.